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Semiconductors

The companies that define the semiconductors industry, each read on the same nine-check website rubric — a 0–100 score with the exact fixes — alongside the concepts, the developments and the questions that shape the field.

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The companies

23 companies in the semiconductors industry, each graded on the nine things that decide whether a buyer or an AI assistant can find and trust them online. Open any name for the full write-up and the specific fixes.

70+ solid   45–69 gaps   under 45 costing customers

Sites we couldn’t reach

16 businesses whose website blocked our scanner — common when a site filters datacenter traffic, and not a sign the site is broken. A blocked site is never scored zero.

Who defines the semiconductors market

The firms, funds and institutions that set the terms in semiconductors — context, not local listings; never scored.

Semiconductors guides

Concepts

Process node

The name of a manufacturing generation — 7nm, 5nm, 3nm, 2nm. Since roughly the 28nm generation the number has been a marketing label, not a measurement of any physical feature on the chip. Compare density, power and performance, never the name.

FinFET

Transistor with a raised fin of silicon wrapped by the gate on three sides. Replaced the planar transistor from around the 22nm generation and carried the industry through the 5nm and 3nm era.

Gate-all-around (nanosheet)

Transistor in which the gate surrounds stacked horizontal sheets of channel on all four sides, giving better electrostatic control than a FinFET. The structure the 2nm-class generations are built on.

EUV and High-NA EUV

Extreme ultraviolet lithography at 13.5nm wavelength, supplied by a single vendor, that made sub-7nm patterning practical. High-NA is the next-generation, larger-aperture version — better resolution, a smaller printable field, and a substantially higher tool price.

Photolithography

Projecting a circuit pattern from a mask onto photoresist on the wafer so it can be developed and transferred into the underlying film. Repeated dozens of times per wafer; the single most expensive step and the one that gates resolution.

Mask, reticle and the reticle limit

The mask (reticle) carries the pattern for one exposure field. The reticle limit is the largest die a single exposure can print — roughly 800 square millimetres on current scanners — which is why very large chips must be split into stitched or separately packaged pieces.

Etch and deposition

The paired subtractive and additive steps. Etch removes material selectively through the resist pattern; deposition (CVD, PVD, ALD, epitaxy) lays down the conductor, dielectric and barrier films. A modern flow runs hundreds of these steps.

CMP

Chemical mechanical planarisation — polishing the wafer flat between layers using a slurry and pad. Without it the stack of interconnect layers would not stay in focus for the next lithography step.

Ion implantation

Firing dopant ions into the silicon to set its electrical character, followed by anneal to repair damage and activate the dopant. Dose and energy control the device threshold.

Wafer size — 200mm vs 300mm

300mm wafers carry roughly 2.25 times the area of 200mm and dominate advanced logic and memory. Much of analog, power and automotive still runs on 200mm, where used-tool scarcity has been a real constraint on adding capacity.

Die

One individual chip on the wafer before it is separated. Die size drives everything downstream — how many fit per wafer, how yield behaves, and what the part can cost.

Yield

The share of die on a wafer that pass test. Because a fab's costs are nearly all fixed, yield is the main lever on cost per good die, and yield learning over the life of a process is where most of the margin comes from.

Defect density and D0

Killer defects per unit area. D0 feeds yield models — Poisson, Murphy, negative binomial — that predict yield from die area and defect density. Bigger die punish the same D0 far harder, which is a core argument for chiplets.

Wafer starts and WSPM capacity

Wafer starts per month is the standard unit of fab capacity. Announced WSPM figures are for a full build-out and rarely describe what a plant can run on the day it opens.

Cycle time and fab utilisation

Cycle time is calendar time from wafer start to finished wafer, typically measured in months for advanced logic. Utilisation is how full the fab is; because fixed cost dominates, a plant running below roughly 80 percent loses money on wafers that are otherwise perfectly good.

Foundry, IDM and fabless

A foundry manufactures to other companies' designs. An IDM designs and manufactures its own products. A fabless company designs and outsources fabrication. The choice determines capex intensity, cycle exposure and how much of the supply chain a company actually controls.

OSAT

Outsourced semiconductor assembly and test — the contract packagers and test houses that take finished wafers and turn them into packaged, tested parts. Concentrated in Asia, and now a bottleneck for advanced packaging as much as wafer capacity is.

Tape-out

The moment a finished design database is released to mask-making. The name survives from the era of magnetic tape. It is a hard commit: after tape-out, fixing anything means new masks and months of calendar.

PDK

Process design kit — the models, rules, symbols and libraries a foundry supplies so a design team can build for its process. The PDK, not the marketing node name, defines what the design can actually do.

IP core and licensing

Pre-designed, pre-verified blocks — CPU and GPU cores, memory controllers, SerDes, interface PHYs — licensed rather than built in-house, usually with an upfront fee plus per-unit royalty. Most of a modern SoC is licensed IP.

EDA flow

The chain of electronic design automation tools that carries a chip from specification to manufacturable layout, plus the verification and sign-off steps at each stage. Three vendors supply nearly all of it.

RTL

Register-transfer level — the hardware description in Verilog, SystemVerilog or VHDL that specifies behaviour cycle by cycle. The level at which designers actually work.

Synthesis and place-and-route

Synthesis compiles RTL into a gate-level netlist against a standard-cell library. Place-and-route positions those cells and wires them together under timing, power, congestion and manufacturability constraints. Together they turn logic into geometry.

DFT

Design for test — scan chains, built-in self-test and compression structures added so a manufactured die can be exercised on a tester. Skimping on DFT means defective parts escape to customers.

Static timing analysis

Exhaustive check that every path meets setup and hold requirements across process, voltage and temperature corners, without simulating vectors. Timing closure is usually the longest pole in a physical design schedule.

DRC and LVS

Design rule check confirms the layout obeys the foundry's geometric rules; layout versus schematic confirms the layout is electrically the circuit that was intended. Both must be clean before a foundry will accept a tape-out.

Silicon bring-up and respin

Bring-up is the lab campaign on first silicon — power, clocks, boot, interfaces, characterisation. A respin is a new mask revision to fix what bring-up found. Respins cost a mask set and a quarter or more of schedule, which is why verification budgets are what they are.

Mask set cost and NRE

Non-recurring engineering is the one-time cost of getting to production — tools, IP, engineering effort and the mask set. Mask sets run from tens of thousands of dollars at mature nodes to the high single-digit millions at the leading edge, and that number alone decides which products can justify an advanced node.

ASP

Average selling price. In semiconductors ASP erosion is the normal condition — prices fall over a product's life while cost falls with yield learning — so plans are built around the gap between the two curves, not around a fixed price.

Gross margin structure

Foundries carry heavy depreciation and live or die on utilisation. Fabless companies carry little fixed cost but pay wafer prices set by someone else. IDMs sit between. The same revenue produces very different economics depending on the model.

Advanced packaging

Everything past the wafer that adds value through integration rather than lithography — fan-out, interposers, stacking, hybrid bonding, embedded bridges. The main axis of performance improvement now that lithographic scaling has slowed and got expensive.

2.5D and 3D integration

In 2.5D, multiple die sit side by side on a silicon interposer or bridge that carries the short, dense connections between them. In 3D, die are stacked vertically with through-silicon vias or direct hybrid bonds. 3D gives shorter connections and harder thermal problems.

CoWoS

Chip-on-Wafer-on-Substrate, TSMC's 2.5D packaging family that mounts logic die and HBM stacks on a silicon interposer. Capacity for this class of packaging, not wafer capacity, has been the practical ceiling on AI accelerator shipments.

Chiplet

A functional die designed to be combined with others in one package rather than shipped alone. Chiplets let a design mix process nodes, dodge the reticle limit and improve yield by keeping individual die small.

UCIe

Universal Chiplet Interconnect Express — an open die-to-die interconnect standard covering the physical layer, protocol and package options, intended to make chiplets from different vendors interoperable. The precondition for a genuine merchant chiplet market.

HBM

High bandwidth memory — DRAM die stacked vertically with through-silicon vias and placed next to the processor, trading capacity per dollar for enormous bandwidth. AI accelerator performance is usually memory-bandwidth bound, which is why HBM supply is contracted years ahead.

Substrate

The organic build-up laminate the die and interposer mount on, carrying signals out to the board. ABF substrates for large packages have been a repeated shortage point, and the supply base sits almost entirely in Asia.

Test, burn-in and binning

Wafer sort screens die before packaging; final test screens packaged parts. Burn-in runs parts hot and biased to force early-life failures out before shipment — standard for automotive and high-reliability grades and a real contributor to unit cost. A bin is the speed, power or feature grade a tested part is sorted into, which turns unavoidable process variation into a product ladder: the same die can ship as a premium or a value part depending on where it lands.

JEDEC and AEC-Q100

JEDEC sets memory and packaging standards, including the HBM and DDR specifications. AEC-Q100 is the automotive stress qualification standard for integrated circuits, with temperature grades from Grade 3 up to Grade 0. Neither is optional in its market.

ISO 26262 functional safety

The road-vehicle functional safety standard, with ASIL levels from A to D. It governs how a component is developed and documented, not merely how it performs, so it shapes design process, traceability and supplier selection from the start.

MSL

Moisture sensitivity level — how long a surface-mount package may sit exposed to ambient humidity before reflow without risking cracking. It drives dry-pack, bake and floor-life handling rules in every factory that touches the part.

RoHS and REACH

EU regimes restricting hazardous substances in electronics and requiring registration and disclosure of chemical substances. Compliance is documentary as much as material, and it flows down the whole supply chain.

Export controls, the Entity List and ITAR

US rules restricting export or re-export of advanced chips, design tools and manufacturing equipment to specified destinations and to companies named on the Entity List, with deemed-export rules that apply to sharing technology with foreign nationals inside the US. ITAR governs defence articles separately. These rules have tightened repeatedly and reach far past defence work.

CHIPS Act funding and clawback

Direct funding, loans and guarantees under the CHIPS and Science Act, awarded against milestones. Awards carry conditions — restrictions on advanced capacity expansion in countries of concern, limits on stock buybacks, upside-sharing provisions — and money can be clawed back if milestones or conditions are missed.

Advanced Manufacturing Investment Credit

The Section 48D federal investment tax credit for semiconductor manufacturing property, originally 25 percent of qualifying investment and raised to 35 percent by the 2025 tax law. For most projects it is worth considerably more than the direct grant.

Allocation and long-term supply agreements

When demand exceeds capacity a supplier allocates output by contract rather than by order date. LTAs lock volume and price years ahead, sometimes with prepayments or capacity reservation fees — the mechanism by which large buyers secured leading-edge and HBM supply.

Design win and socket

A design win is a customer committing your part into a product design; the socket is the specific position on the board it occupies. Revenue follows the customer's production ramp, often a year or more later, and displacing an incumbent socket means re-qualification the customer would rather avoid.

BOM cost

The bill-of-materials cost of every component in the finished product. Chips are sold into a BOM budget, so a part is judged on what it lets the designer remove elsewhere — an integrated SoC that eliminates three discrete devices wins at a higher unit price.

What’s happening

• AI accelerator demand has pushed advanced packaging and memory, rather than wafer capacity, to the front of every supply conversation. Silicon interposer capacity of the CoWoS type and HBM stack supply are the two lines in the flow that have repeatedly gated shipments, and both are contracted well ahead of delivery -- SK hynix reported finalising long-term agreements with around ten customers alongside its HBM4 ramp, and TSMC has CoWoS in production at 5.5 reticle sizes with a 14-reticle generation, enough for roughly ten compute dies and twenty HBM stacks, targeted for 2028. Calling packaging the binding constraint is trade-press characterisation rather than a foundry statement, but the direction is well supported, and packaging and memory commitments remain the single most useful thing to watch when judging whether an AI silicon roadmap is credible. 2026-08 source ↗
• Memory has been pulled into the same vortex. HBM commands far more wafer area and packaging effort per bit than conventional DRAM, so the shift of memory capacity toward HBM has tightened supply and lifted pricing for ordinary DRAM used in servers, PCs and embedded products. JEDEC published the HBM4 standard, JESD270-4, in April 2025, with a JESD270-4A revision in December 2025 and a separate SPHBM4 standard following in 2026. HBM4 is no longer entering qualification -- SK hynix began mass shipments in the second quarter of 2026 with further ramp through the second half -- which raises both bandwidth and the stack complexity that suppliers must yield on. 2026-08 source ↗
• CHIPS and Science Act awards moved from announcement to construction, and the construction is where timelines have proved elastic. Commerce finalised up to $4.745 billion in direct funding for Samsung's Texas operations in December 2024 -- itself a reduction from the $6.4 billion preliminary memorandum of April 2024, alongside Samsung trimming its stated investment from $44 billion to $37 billion -- covering two leading-edge logic fabs and an R&D fab in Taylor plus expansion of the existing Austin fab, with Texas layering its own money on top. State the Taylor status carefully: the equipment move-in ceremony was held in April 2026, Samsung has recast its end-2026 milestone from starting production to completing mass-production preparations, and volume output on its SF2 2nm-class node is reported as slipping into 2027, with Tesla the anchor customer under a foundry agreement announced in July 2025. There is no evidence the Samsung award has been renegotiated or converted. Treat any published production date as in flux and cite the company's own announcements. 2026-08 source ↗
• The federal incentive mix shifted decisively toward the tax credit. The IRS states that the Section 48D Advanced Manufacturing Investment Credit is 25% of qualified investment for property placed in service through December 31, 2025 and 35% for property placed in service thereafter, attributing the increase to the Working Families Tax Cuts Act of 2025 -- so the higher rate does not reach 2025 placements, and the statute is named differently in various tax-advisory summaries, which is worth checking before citing. For most large projects the credit is worth more than the direct grant. The administration also restructured several CHIPS awards, most visibly with Intel: on August 22, 2025 Intel announced an $8.9 billion federal investment for 433.3 million primary shares at $20.47, a 9.9% common stake, funded by $5.7 billion of undisbursed CHIPS grants plus $3.2 billion from the Secure Enclave program, bringing total government investment to $11.1 billion. That precedent changed how companies model the cost of accepting federal money. 2026-08 source ↗
• Export controls on advanced chips and semiconductor equipment tightened in successive rounds from October 2022 onward, extending from the chips themselves to the tools, subsystems, software and services used to make them, and to a growing Entity List. The most important recent change runs the other way in form but not in substance: on May 13, 2025 Commerce rescinded the Biden-era AI Diffusion Rule two days before its compliance date, replacing a worldwide tiered licensing framework with targeted measures -- guidance on Huawei Ascend chips and general-prohibition exposure, guidance on US AI chips used to train Chinese models, and supply-chain diversion-prevention guidance -- while leaving the 2022 and 2023 controls intact. Compliance now reaches ordinary commercial teams: deemed-export rules under the EAR govern who may see technical data, and end-use screening has become a standard part of selling advanced parts. 2026-08 source ↗
• Competition at the leading edge is genuinely three-way for the first time in years, and two of the three are shipping. TSMC states its N2 technology started volume production in the fourth quarter of 2025 using first-generation nanosheet transistors. Intel is running 18A in high-volume manufacturing at Fab 52 in Chandler with RibbonFET and PowerVia, shipping Panther Lake -- so Intel is past trying to re-establish itself and into delivering product. Samsung Foundry is pushing its own SF2 2nm-class node with customer commitments tied to its Texas capacity, but that capacity is still in equipment installation and qualification rather than production. The interesting question is no longer who has the best transistor on paper but who can yield it at volume and package it. 2026-08 source ↗
• High-NA EUV has moved from research into production. ASML reported in July 2026 that High NA EUV had reached readiness in a production environment, with Intel Foundry in high-volume manufacturing on 18A and specific layers dual-qualified in Oregon, product shipping at yields matched to the standard NXE platform, on the second-generation TWINSCAN EXE:5200B. The optics change the practice: numerical aperture rises from 0.33 to 0.55 and the anamorphic design was chosen specifically so chipmakers could keep conventionally sized reticles, at the cost of exposure fields half the size of their predecessors -- which doubles exposures and forces field stitching and design partitioning changes rather than mask-blank changes. Tool pricing is not published by ASML; the figures in circulation are press estimates. Not every manufacturer is adopting on the same schedule, and the divergence is one of the clearer strategic bets visible in the industry right now. 2026-08 source ↗
• Chiplets have gone from a technique one company used internally to an industry architecture, and UCIe is the standardisation effort that would make a merchant chiplet market possible. The specification has advanced through successive revisions -- 1.0 established the die-to-die stack, 1.1 added automotive and reliability features with runtime health monitoring, 2.0 added manageability, debug and 3D packaging support, and the current 3.0 revision doubles data rates to 48 and 64 GT/s -- with each release backward compatible. Real multi-vendor chiplet interoperability is still ahead of the ecosystem, but the direction is no longer in doubt. 2026-08 source ↗
• RISC-V adoption has moved past experimentation into shipping product, helped by the ratification of standard application profiles that give software vendors a stable target. RISC-V International ratified the RVA23 profile in October 2024, making the Vector and Hypervisor extensions mandatory -- which is the substantive reason operating system and toolchain vendors could commit, and why the consortium frames it as cutting vendor development and maintenance cost through portability. It shows up first in embedded controllers, storage and AI accelerator control planes rather than in general-purpose application processors, and its strategic appeal -- an instruction set no single company or jurisdiction controls -- has grown as export controls have tightened. 2026-08 source ↗
• The automotive and industrial chip market worked through an inventory correction that ran almost exactly out of phase with AI strength, and it has now largely recovered -- which is a correction to a lot of content still written in the present tense. After the shortage years customers over-ordered, and the resulting destocking hit MCU, analog and power suppliers hard through 2023 to 2025 while accelerator and HBM demand went the other way. By mid-2026 the bellwether has flipped: Texas Instruments reported second-quarter 2026 revenue up 13% sequentially and 23% year over year with broad growth led by industrial, data center and automotive. The residual 2026 problem is the opposite one -- selective tightness in silicon carbide MOSFETs, safety-rated 32-bit MCUs and IGBT modules. 2026-08 source ↗
• Power and water have become gating factors for fab siting in Texas. Large fabs and the data centres that consume their output are arriving in the ERCOT footprint faster than interconnection can be granted, and the Texas legislature responded with SB 6 in the 2025 regular session -- signed and effective June 20, 2025 -- governing planning, interconnection, operation and cost allocation for large electrical loads, generally those at or above 75 MW, including mandatory curtailment and firm load-shed obligations during scarcity and review of co-location arrangements. Provisions phase in rather than all landing on one date, and the law governs large loads generally, with data centres the dominant driver rather than fabs. Water is the quieter constraint: fabs use very large volumes of ultrapure water, and reclaim rates and municipal supply agreements are now negotiated up front rather than assumed. 2026-08 source ↗
• The workforce shortage is the constraint every Texas project names. A fab needs technicians, operators and equipment engineers in far greater numbers than it needs PhDs, and those roles take one to two years to train rather than six. Austin's response has been institutional: in March 2024 UT Austin, the Austin Community College District and the Texas Institute for Electronics launched a joint Semiconductor Training Center combining hands-on technical training with academic theory, with first programs targeted for January 2025. Separately, the Texas Semiconductor Innovation Fund, created by the Texas CHIPS Act in June 2023 with an initial $698 million appropriation and a further $250 million added in June 2025, makes grants to higher-education institutions and businesses for semiconductor research, manufacturing and design -- workforce is a policy goal of the Act, but the fund's own grant categories are research, manufacturing and design, so do not attribute the training centre's funding to it. 2026-08 source ↗
• Reshoring is moving downstream from wafers to packaging and substrates, which is where the real dependency sits. Advanced packaging, test and organic substrate manufacturing are heavily concentrated in Asia, and building any of it in the US means new facilities, new supplier relationships and a trained assembly workforce. The Texas Institute for Electronics at UT Austin was awarded $840 million by DARPA in July 2024 under the Next Generation Microelectronics Manufacturing programme to build a national open-access R&D and prototyping fab for 3D heterogeneous integration serving Department of Defense microelectronics, on top of a $552 million state appropriation -- roughly $1.4 billion in total, and a direct attempt to build that capability in Central Texas. 2026-08 source ↗
• The Central Texas cluster now has depth across the whole stack rather than one anchor tenant, though several commonly repeated claims need qualifying. Samsung runs long-established Austin fabs and the Taylor site. NXP's US headquarters is in Austin at the 155-acre, 1.5-million-square-foot Oak Hill campus built for Freescale in 1984 and acquired with Freescale in 2015, plus two Austin wafer fabs -- but NXP listed that campus for sale in December 2025 and is relocating within northwest Austin, so 'largest US campus' is in flux even though the headquarters stays. AMD's Lone Star campus in Austin is 870,000 square feet on 58 acres with more than 2,500 employees, and AMD's own description is its largest non-manufacturing campus, not its largest US site -- its headquarters is in Santa Clara. Silicon Labs and Ambiq are headquartered here, Applied Materials and Tokyo Electron run Austin operations, and Texas Instruments' Sherman and Richardson fabs sit at the other end of I-35. That combination -- leading-edge manufacturing, mature-node manufacturing, fabless design, equipment supply and a funded research and packaging institute in one metro -- is rare, and it is the single strongest local content angle available. 2026-08 source ↗

Questions people ask

What is the difference between a foundry, an IDM and a fabless company?

foundry manufactures wafers for others, IDM designs and manufactures its own products, fabless designs and outsources manufacturing -- and note the lines blur now that IDMs sell foundry services

What does a process node number like 3nm or 2nm actually mean?

say plainly that node names stopped corresponding to any physical dimension years ago and are marketing labels for a generation; compare density, performance and power from the vendor's own disclosures instead

What is an OSAT and what does it do?

outsourced semiconductor assembly and test -- the companies that package the die and test the finished part; note that advanced packaging has made this layer strategically important rather than a commodity back end

What is yield and why does it dominate chip economics?

explain good die per wafer against total die, the relationship to defect density and die size, and why a large die is punished twice -- fewer die per wafer and lower yield on each

What is advanced packaging and why does everyone talk about CoWoS?

describe packaging as the step that connects multiple die and memory stacks at high bandwidth, and CoWoS as the interposer-based family that AI accelerators depend on -- which is why packaging capacity, not wafer capacity, has been the bottleneck

What is a chiplet and how is it different from a system on chip?

a chiplet splits what would have been one monolithic die into several, each on the node that suits it, connected in package -- it improves yield and mixes process technologies at the cost of packaging complexity

What is UCIe and why does it matter?

describe it as the die-to-die interconnect standard that would make a merchant chiplet market possible, note it has advanced through successive revisions, and be honest that multi-vendor interoperability is still ahead of the ecosystem

What is HBM and why is it in short supply?

high bandwidth memory stacks DRAM die vertically next to the processor; it consumes far more wafer area and packaging effort per bit than standard DRAM, so shifting capacity to HBM tightens ordinary DRAM too

What is EUV lithography and what is High-NA?

extreme ultraviolet patterning at 13.5nm wavelength; High-NA raises numerical aperture for finer features at the cost of a smaller printed field, which forces mask and design-partitioning changes

What is a tape-out and what is NRE?

tape-out is releasing the final design for mask making; NRE is the one-time engineering and mask-set cost before a single sellable part exists -- and it rises sharply at leading-edge nodes

What is a PDK and why can I not move a design between foundries?

the process design kit encodes the foundry's device models and rules; a port means re-characterization, re-verification and often re-layout, which is why second-sourcing at the leading edge is rare

What is AEC-Q100 and why does automotive qualification take so long?

describe the stress-test qualification grades by temperature, and connect it to ISO 26262 functional safety and PPAP -- the calendar time is the qualification and the customer's own validation, not the silicon

How long are semiconductor lead times right now?

explain that lead times diverged by segment -- leading-edge AI parts and their packaging and HBM allocated far out, while mature-node analog, MCU and power parts came down through the inventory correction -- and say the only reliable number is the current quote from the supplier or franchised distributor for your specific part

Why did the chip shortage end for some parts and not others?

explain the out-of-phase cycles -- customers over-ordered mature-node parts during the shortage and then destocked through 2023-2025 while AI demand hit packaging and memory capacity -- and note the 2026 state: the broad correction has worked through, with residual tightness now concentrated in silicon carbide MOSFETs, safety-rated 32-bit MCUs and IGBT modules

What is allocation and how do long-term supply agreements work?

describe allocation as the supplier rationing constrained capacity by customer, and LTAs as volume and price commitments that buy priority -- and name the risk honestly, that a take-or-pay commitment becomes a liability when demand turns

Should I design for a leading-edge node or a mature node?

frame it on volume against NRE, power and performance requirements, expected product life and supply security; the crossover depends on the reader's volume and mask cost quote, which is not public

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